This invention relates generally to the art of testing packaged integrated circuits, and, more specifically, to techniques for developing test programs useful with existing automatic test equipment for testing such circuits.
The design and fabrication of a new digital integrated circuit involves a series of sequential steps. First, using available software design tools, a schematic diagram of the desired integrated circuit is constructed. Secondly, the operation of the designed circuit is simulated on a computer with available simulation software. Such a simulation involves performing a number of discreet tests on the designed circuit. Each test includes application of a sequential series of signals (test vectors) to the inputs of the circuits, and then comparing the outputs of the circuits with expected output test vectors. If the simulation does not provide the desired results, the circuit design schematic is altered and the simulation again performed. This cycle is repeated until the simulation demonstrates that the circuit is providing the desired results.
Once the designer is satisfied that the circuit schematic is correct and will result in an integrated circuit that operates in the desired manner, a third basic step in the design cycle is to lay out the masks, using available software tools, that are to be used in fabricating the integrated circuits. Once the masks are completed, the tooling necessary for manufacture of the integrated circuits is made. A large number of the circuits are formed at one time on a single semiconductor wafer. The wafer is then separated into individual circuit die (chips) which are then individually packaged. Each package has many pins, which can number from as few as a dozen to as many as a hundred or more, which are electrically connected to various points on the internal integrated circuit chip.
It is usual that each circuit chip is tested at least once by the manufacturer before shipment to the customer. This routine is generally always performed on the finished, packaged product, but may additionally be performed on a circuit die before packaging. Automatic test equipment (ATE) is commercially available for performing such tests. The Sentry model 20/21, available from Schlumberger, is among the most popular test equipment. Each different model of ATE available from various manufacturers operates somewhat differently and has specific, unique requirements for an input test program that will cause the equipment to perform desired tests on a specific integrated digital circuit.
Initially, such ATE was programmed essentially from scratch for each new integrated circuit that was desired to be tested on the equipment. That is, a number of individual tests were designed by providing a list of input test vectors (signals) and a set of desired output test vectors directly in the specific format required by an individual piece of equipment to be utilized. More recently, various software tools have become available to automate at least a portion of the design cycle. Such software begins with the simulation test vectors used by the circuit designer to simulate several specific operations of the logic being designed. Available test equipment, however, is far less flexible than logic simulation programs. That is, the test engineer designing a test program to be implemented on the Sentry model 20/21, or other test equipment, is faced with many limitations and restrictions with which the circuit designer does not have to deal. As a result, existing software techniques for automatically converting the simulation tests into a form that can be executed on an actual circuit with ATE are not fully automatic. A great deal of work still remains for a test engineer which can take weeks or months to design and debug a test program for a new circuit. Since the ability to test circuits must exist before the circuits can be sold, a semiconductor manufacturer often must delay introduction of a new product, that is otherwise manufacturable, in order to allow time for an appropriate test program to be developed.
Accordingly, it is a primary object of the present invention to provide an improved software tool for developing a test program for a new integrated circuit product in a reduced amount of time and with less individual test engineer effort being required.
It is an additional object of the present invention to provide an improved test program generation software that is flexible and easy to use, provides abundant diagnostic aids, conserves memory, and has a high speed of execution.